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wb_lpc_latest.tar.gz
- Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
lpc
- LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
LPC_Peri
- LPC总线中目标机的vhdl代码，Low pins bus-Low pins bus
Vme_Interface
- 这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX
LPC2DDR2
- Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
LPC_Host
- LPC总线，主机模块代码，VHDL语言描述-LPC bus, the host code, VHDL language descr iption
module_lpc
- LPC接口的VHDL语言实现，可以用于TPM的开发，以及基于FPGA的设计-LPC interface language realization of VHDL, can be used for the development of the TPM, as well as the design based on FPGA
LPCSPEC
- LPC总线规范，2002年8月1.1版，VHDL、固件编程必看-LPC bus specification, version 1.1 in August 2002, VHDL, firmware programming must see
LPC-program-CPLD
- 使用quartus开发。该程序通过VHDL语言实现了LPC时序。控制了2个LED数码管，通过读取LPC总线的上BIOS的数据，实现了计算机排故的POST卡功能。-Use quartus development. The program through the VHDL language to achieve a LPC timing. Control of the two LED digital tube, by reading the BIOS on the LPC bus data to a
LPC post
- 使用VHDL语言通过LPC接口实现的post卡功能，用于debug
lpc_peri
- LPC periph，VHDL and verilog version design， lattice